1. Field of the Invention
The present invention relates to a technique for creating an analysis model and a technique for creating a circuit board model. The present invention particularly relates to techniques for creating an analysis model and a circuit board model for which a bypass capacitor can be added with a light workload that does not involve any change to CAD data.
2. Description of the Related Art
Development of a circuit board such as a printed circuit board (PCB), a multi-tip module (MCM) and an LSI package involves creation of CAD data by performing the circuit board packaging design utilizing circuit board design CAD, and creation of an analysis model from the CAD data and property data of parts. Then, the circuit operation is analyzed by performing a simulation with using a circuit simulator in accordance with the analysis model.
The result of the analysis includes, for example, the impedance in each band and the result of the analysis is then evaluated by the user. When it is rated as power-supply noise is large, certain means needs to be adopted to reduce the power-supply noise. The means for noise reduction is assumed herein as the use of a bypass capacitor.
The addition of a bypass capacitor, however, requires a significantly long time (from a few hours to more than a hundred and several tens of hours) for a series of processes including the change of the circuit board design and creation of the analysis model.
Japanese Patent Application Publication No. 2006-228252 “SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD, AND READABLE RECORDING MEDIA” presents a technique for adding a bypass capacitor near the noise source within a circuit block in order to reduce power-supply noise on a circuit board.
However, the technique presented in the patent document still does not solve the above-mentioned problem that the development requires a significantly long time.